1. Field of the Invention
This invention relates to electronic circuits used to delay signals and more specifically to circuits used to delay the turn-on of a power transistor in a bridge configuration.
2. Description of the Relevant Art
The problem addressed by this invention is encountered when power transistors are used to drive a prior art bridge configuration such as in FIG. 1. The bridge configuration 2 can be used to power motors, drive solenoids, and the like. The bridge configuration 2 is characterized by the high side driver transistor 4 being connected in series to a low side driver transistor 6 across the voltage of a power supply. In this configuration, node 12 is driven to the power supply voltage when the high side transistor 4 is on and transistor 6 is off. Conversely, node 12 is sunk to ground when high side transistor 4 is off and lowside transistor 6 is on. If the high side and low side transistors are both turned off, then node 12 is at a high impedance state. However, if both high side 4 and low side 6 transistors are turned on, then the transistors are shorting the power supply voltage to ground which would draw an excessive amount of current and would damage one or both of the transistors. The bridge configuration is never used with both high side and low side drivers on at the same time because of the potentially disastrous results. Consequently, it is common to use a delay circuit as part of the control logic in the control block 9 to prevent the turn-on of one driver transistor until the other driver is turned off. In principle, one of the drivers is turned off while the other driver is turned on, but only after the delay circuit has delayed the turn-on by an amount of time which will guarantee that the other driver is in fact turned off.
FIG. 2 illustrates a prior art delay circuit 20 used in the control block 9 of FIG. 1 for delaying the turn-on of the driver transistors 4 or 6. In delay circuit 20, p-channel transistor 22 and n-channel transistor 24 form a first inverter. Similarly, p-channel transistor 30 and n-channel transistor 32 form a second inverter. The gates of transistors 22 and 24 form the inputs of the first inverter and the drain of transistor 30 and the drain of transistor 32 form the output of the second inverter. In operation, as the input signal goes from a low voltage to a high voltage, transistor 22 turns off and transistor 24 turns on. As a result, the voltage at node 23 drops from near Vdd to near ground. Consequently, the charge on capacitor 28 is drained through resistor 26 and transistor 24. The rate of discharge is determined by the size of resistor 26 and capacitor 28 as is known in the art. When the voltage on node 31 reaches approximately 2.5 volts, transistor 32 turns off and transistor 30 turns on which raises the voltage at node 33. The time delay can be approximated by the equation: EQU T.sub.delay =(R26)(C28)1n(1-Vdd/V.sub.threshold)
Therefore, the rising signal on the input of the delay circuit 20 is passed on to the output of the delay signal 33, but only after the delay created by the time constant of resistor 26 and capacitor 28. However, prior art delay circuit 20 is limited since it often requires relatively large capacitors and/or resistors to obtain long delays. The requirement of a large capacitor or resistor is undesirable since a large capacitor or resistor typically requires large amounts of silicon on an integrated circuit or requires an external connection for an external capacitor. Since the cost of a integrated circuit is directly proportional to the die size, it is desirable to reduce the size of a circuit whenever possible.